(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes for forming buried contacts.
(2) Description of Prior Art
Very large scale integrated circuit technology (VLSI) comprises the formation of isolated semiconductor devices within the surface of silicon wafers and interconnecting these devices with wiring layers above the surface. This interconnection system usually consists of two or more levels of interconnection metallurgy, separated by insulation layers. The first level of interconnection is used to define small fundamental circuits, for example, a simple TTL gate comprised of two bi-polar transistors and two resistors. Memory cells, in particular, require many such local interconnect ions.
A static-random-access-memory (SRAM) cell design which has gained particular favor in recent times is the poly-load cell shown schematically in FIG. 1. This cell utilizes polysilicon load resistors in place of the metal-oxide-silicon-field-effect-transistors (MOSFETs) used in earlier n-channel MOS (NMOS) and complementary MOS (CMOS) designs.
With only four resistors and the high-valued polysilicon resistors fabricated in a second polysilicon level above the cell, a much smaller amount of space is required. The power consumption of the poly-load cell is considerably less than the NMOS SRAM. Unlike CMOS arrays, poly-load cell arrays can be fabricated entirely within a single p-type well and supported by full CMOS peripheral circuitry.
The quest for miniaturization and the driving need for higher and higher density of memory cells has fueled the development of local-interconnect technology. The success and extensive use of polysilicon as the MOSFET gate material has played a dominant role in this development and, in the sub-micron technology of today, it has become the most important material used for forming these connections. Previous technology used an aluminum alloy for short wiring runs such as from a gate electrode to an adjacent drain. These links were referred to as butted contacts because the contact window was opened to expose both the polysilicon and the adjacent drain. The buried contact came into existence with the use of polysilicon. When in-situ doped polysilicon is deposited over a thin gate oxide layer to form the transistor gate, it is simultaneously deposited into openings in this oxide which expose a portion of the active region adjacent to field oxide of the MOSFET device. Dopant from the polysilicon can then be driven into the silicon forming an extension of the active region under the polysilicon, thereby forming an ohmic contact between the polysilicon and the active region. The polysilicon extends over the thick field oxide region and can be continuous with a polysilicon gate.
The poly-load cell in FIG. 1 has local interconnects formed with buried contacts where the polysilicon gates of the driver transistors M1 and M2 are connected to the drain regions of the access transistors M3 and M4. In the conventional SRAM array design, these buried contacts often lie in close proximity to each other and to similar buried contacts of adjacent cells. For the newer sub-half micron SRAM designs, the spacings between buried contacts approach 0.5 to 1.0 microns.
In FIG. 2 there is shown the top view of a portion of an SRAM array with buried contacts of adjacent cells lying in close proximity 54. Polysilicon gate stripes 56 and 58 are connected to drain regions 60 and 62 by buried contacts 50 and 52.
A cross-section of the region denoted by Y1-Y2 is shown in FIG. 3A. Tightly packed designs of contemporary SRAMs have reduced the spacing 54 to the extent where current channeling between buried contacts under the field oxide FOX has become a serious concern. The n+ regions 60 and 62 under the buried contact are formed by an ion implantation after the buried contact regions 50 and 52 have been exposed using standard photolithographic techniques. A deep boron implant 64 is performed at this time to improve buried contact isolation. However, the contemporary implant, which is performed at a 0.degree. to 7.degree. tilt angle is inadequate for preventing current leakage between the buried contacts 50 and 52 when the spacing 54 falls below 1 micron.
Oblique or Large-Angle-Tilt (LAT) ion-implants have found numerous applications in sub-micron technology. They have been successfully used to provide fully overlapped lightly-doped-drain (LDD) structures for 1/4 micron MOSFETS. Here the LDD is implanted under the polysilicon gate by directing the dopant ions obliquely at the edge of the gate. Gonzalez U.S. Pat. No. 5,439,835 has shown that LAT can be used to deposit boron under one side of a polysilicon gate in a DRAM to provide punchthrough protection without compromising the other side which faces the storage node. At the same time boron is deposited through the center region of the field oxide to form a channel stop. Roberts U.S. Pat. No. 5,240,874 similarly reports an oblique channel stop implant into the silicon below the field oxide to control channel width for an SRAM process. This implant is accomplished through the field oxide and reaches the area below the birds-beak by virtue of a high implant angle. An additional masking step is required for this procedure to protect the device regions external to the field oxide.